Reducing Supply Voltage in Nanoscale Transistor with Ferroelectric Materials

Introduction

Fig. 1: Vsupply vs. technology node. (Image Source: J. Kim, after Lee et al. [1])

The semiconductor industry has long relied on Moore's Law to drive advancements in transistor scaling, achieving improvements in both performance and energy efficiency with each new generation. However, as transistors approach near-atomic dimensions, physical and quantum mechanical constraints have created significant challenges for continued scaling. One of the most critical obstacles is the stagnation of supply voltage to transistor's gate and drain terminals (V_supply), which has been scaled down very slowly in recent several technology generations, as shown in Fig. 1. [1] Reducing V_supply further has proven to be exceptionally difficult, yet its reduction is crucial for minimizing power consumption in computational chips, as both dynamic power and off-state power are directly influenced by V_supply. Here we explore the fundamental reasons why V_supply scaling has stalled under conventional scaling approaches, such as Dennard scaling law, and examine the potential of ferroelectric (FE) materials for their usage as gate dielectrics in next-generation nanoscale devices to overcome this limitation. [2]

The Role of V_supply in Determining Power Consumption of the Chip

Reducing V_supply is crucial to minimize power consumption in modern transistors, as it directly affects both dynamic and off-state power consumption. The dynamic power, the energy consumed during transistor switching, is expressed as:

where α is the activity factor representing the fraction of clock cycles during which a circuit node switches (transitions) from 0 to 1 or from 1 to 0, C is the capacitance, and f is the operating frequency. The quadratic dependence on V_supply means even modest reductions in V_supply yield significant savings in dynamic power. For example, 10% reduction in V_supply results in approximately 20% reduction in dynamic power consumption. Also, the off- state power consumption, which occurs when transistors are nominally off but still exhibit off-state channel leakage current, is given by

where I_off is the channel leakage current per transistor and N denotes the total number of transistors in the chip. The off-state power consumption has become a significant concern, particularly in modern chips containing over a billion transistors. Consequently, reducing V_supply plays a crucial role in lowering the total power consumption in the chip by minimizing the P_off-state.

Why V_supply Scaling Is Extremely Challenging?

One of the primary reasons V_supply scaling faced its limit is the inability to scale down the threshold voltage (V_Th) using conventional methods. V_Th, the minimum voltage needed at the gate to turn on the transistor and allow current to flow between the source and drain, is fundamentally governed by the bandgap of the semiconductor material. For silicon (Si) MOSFETs, V_Th typically falls within the range of approximately 0.4 V. [3] While there have been efforts to replace silicon with smaller bandgap materials such as germanium (Ge), adopting these materials in commercial applications remains extremely challenging. [4] The primary obstacles include increases in manufacturing complexity and cost, which hinder their feasibility in large-scale production. In this context, further reduction of V_supply cannot provide sufficient overdrive voltage at the gate (V_supply - V_Th), leading to a significant deterioration in on-state current (I_on), which is critical for the high switching speeds required in modern chips. [3] Note that I_on is expressed by

where Q is total charge accumulated in the channel and v_av is the average carrier velocity in the channel.

Ferroelectric Materials as a Gate Dielectric

Fig. 2: Energy landscape of FE, DE (depolarization). (Image Source: J. Kim, after Cheema et al. [5])

Hafnium-based FE materials have garnered significant attention for their potential use as gate dielectrics in next-generation technology nodes. Recent studies have demonstrated that, when properly connected in series with dielectric materials, FE materials can exhibit a negative capacitance effect. [1,5-7] As shown in Fig. 2, FE materials typically have a double-well energy landscape in Gibbs free energy vs. polarization plot. It can be flattened with the presence of the dielectric materials in series, effectively increasing the permittivity of the overall system. [7] This phenomenon results in a remarkable and unconventional outcome: the total capacitance of the two capacitors in series can be greater than the capacitance of either individual component, defying conventional expectations. For example, ultrathin ferroelectric HfO₂-ZrO₂ (HZH) superlattice gate stacks with a thickness of approximately 2 nm has been demonstrated. [5] These stacks exhibit an equivalent oxide thickness (EOT) of about 6.5 Å, even when conbined with 8.5 Å-thick native silicon dioxide (SiO₂). Note that EOT is a measure used to describe the thickness of a gate dielectric material in terms of an equivalent thickness of SiO₂ that would provide the same electrical performance, calculated by

where ε_SiO2 is permittivity of the SiO₂, ε_high-k is permittivity of the high-k material, and t_high-k is thickness of the actual high-k dielectric. This unconventional reduction in EOT can result in significant increase in gate capacitance and I_on, creating the opportunity to further reduce V_supply without compromising switching speed. Furthermore, this achievement is particularly significant when considering that the new gate dielectric process is fully compatible with the conventional industry-standard ALD process. This compatibility ensures that the process does not increase manufacturing complexity or costs, making it highly feasible for large-scale integration.

EOT Comparison with Conventional High-k Gate Dielectrics (HfO₂)

In modern transistor, HfO₂ with a thickness of approximately 2 nm is widely used as a gate dielectric. With a relative permittivity of around 16, its EOT is approximately 1.35 nm, assuming a native SiO₂ layer with a relative permittivity of 4 and a thickness of 8.5 Å. However, replacing conventional HfO₂ with an HZH superlattice can reduce the EOT to 6.5 Å, nearly doubling the effective capacitance while maintaining the same physical thickness. [5] This remarkable capability of ferroelectric materials to increase the capacitance provides the flexibility to reduce V_supply, thereby minimizing power dissipation of the chip. For instance, around 20% reduction in V_supply could be achieved with a corresponding 20% enhancement of capacitance using a ferroelectric gate dielectric such as HZH superlattice stacks, which would theoretically result in around 20% reduction of both P_dynamic and P_off-state, improving the energy efficiency of the entire chip.

Conclusion

The scaling of V_supply has become increasingly challenging in the post-Moore's Law era. Ferroelectric materials like HZH, with their unique negative capacitance effect, provide a promising solution to overcome the limitations of further V_supply reduction. This essay has explored the potential of these materials as innovative gate dielectrics for next- generation devices. Particularly in terms of energy efficiency, the integration of ferroelectric materials holds the potential to significantly reduce the power consumption of data centers and other computational systems by enabling lower switching voltages in transistors, paving the way for more sustainable and high-performance technologies. Furthermore, the compatibility of this process with current industry standards, such as ALD for gate dielectric deposition, enhances its feasibility, making this technology even more promising.

© Jeongkyu Kim. The author warrants that the work is the author's own and that Stanford University provided no input other than typesetting and referencing guidelines. The author grants permission to copy, distribute and display this work in unaltered form, with attribution to the author, for noncommercial purposes only. All other rights, including commercial rights, are reserved to the author.

References

[1] M. H. Lee et al., "Physical Thickness 1.x nm Ferroelectric HfZrO_x Negative Capacitance FETs," IEEE 7838400, International Electron Devices Meeting (IEDM), 3 Dec 16.

[2] R. H. Dennard et al., "Design of Ion-Implanted MOSFET's With Very Small Physical Dimensions," IEEE 1050511 IEEE J. Solid-State Circuits 9, 256 (1974).

[3] J. D. Plummer and P. B. Griffin, Integrated Circuit Fabrication: Science and Technology (Cambridge University Press, 2024).

[4] K. C. Saraswat, "Germanium: Back to the Future," in 75th Anniversary of the Transistor, ed. by A. Nathan, S. K. Saha, and R. M. Todi (Wiley-IEEE Press, 2023).

[5] S. S. Cheema et al., "Ultrathin Ferroic HfO₂- ZrO₂ Superlattice Gate Stack For Advanced Ttransistors," Nature 604, 65 (2022).

[6] D. Kwon et al., "Negative Capacitance FET With 1.8-nm-Thick Zr-Doped HfO₂ Oxide," IEEE 8695029, IEEE Electron Dev. Lett. 40, 993 (2019).

[7] A. I. Khan et al., "Experimental Evidence of Ferroelectric Negative Capacitance in Nanoscale Heterostructures," Appl. Phys. Lett. 99, 113501 (2011).