Electrical Interconnect Energy Overhead

Lita Yang
December 11, 2015

Submitted as coursework for PH240, Stanford University, Fall 2015

Growth in Electrical Interconnect Energy Overhead

Fig. 1: Interconnect energy optimization techniques at the different levels of the system design hierarchy. (Source: L. Yang)

Electrical interconnects have become the limiting factor for energy and performance improvements in modern systems on chips (SoCs) and microprocessors. While CMOS transistor scaling has allowed for increased integration and enhancements in computational performance, the immense energy cost to move data around in a system can far exceed computational energy. In 2012, Esfandyarpour reported that electrical interconnects consumed more than 50% of the total power in a microprocessor. [1] Without changing the conventional design philosophies, this ratio is expected to reach up to 80% of microprocessor power in 2017 as interconnect dimensions reach the nanometric regime from CMOS technology scaling. [2] In fact, recent literature already cite numbers for wire and interconnect energy overheads well over 90% in advanced process nodes for data-intensive computing platforms. [3,4] Given demands for higher data bandwidths and processing power, coupled with the challenges associated with improving data center energy inefficiency, energy-efficient communication is a primary concern in large-scale integrated circuit (IC) design and a major contributor to wasteful electronic energy consumption. [5]

Why Interconnects Consume So Much Energy

With next generation SoCs expected to have more than a billion transistors, ensuring efficient and reliable data communication becomes increasing difficult. Two major reasons why interconnect energy has become a dominant source of energy consumption in modern SoC design can be attributed to: (1) increasing chip sizes and (2) the design complexities and energy overheads in maintaining sufficient reliability. A large share of the energy consumption is due to the long, high-capacity wires crossing large IC dies and connections to multiple subsystems, a trend that is expected to continue increasing as demand for larger die sizes and more subsystems continues to grow. [6] Many technological factors stemming from CMOS technology scaling challenge design of reliable, low-energy communication. Process variation and reduced signal margins due to continued supply voltage scaling makes interconnects more susceptible to noise sources such as crosstalk, power supply noise, radiation induced defects, and electromagnetic interference. [7] The result of all this is inefficient over margining in the design choice of signal levels and timing, reduced yields, and higher susceptibility to both static and transient errors. [8] Conventional design methodologies which seek to eliminate all these noise related errors are becoming very costly, if not impossible, when considering practical limits for power-constrained applications such as mobile devices. This fuels the need for a major paradigm shift towards designing for error tolerance instead of error avoidance, as stressed in Raghunathan et al., if future systems hope to improve energy efficiency. [7]

Interconnect Energy Reduction Techniques

Several techniques have been proposed to design more energy-efficient interconnects, while maintaining sufficient performance and reliability without significant implementation overhead. Achieving an energy-efficient and reliable SoC interconnect architecture requires the use of structured, interconnect-oriented design methodology at all abstractions of the system hierarchy, as shown in Fig. 1. This section aims to briefly highlight some of the techniques that have been used at each level in Fig. 1, along with the major issues to consider for practical implementation.

System Level Techniques

At the system level, embedding communication-based power management can help regulate interconnect energy overhead. While integrating power management at the system-level helps eliminates the need for a separate power entity and can better regulate timing schedules of different components, the downside is a performance degradation and increase in area overhead. Similarly, adaptive supply voltage links or dynamic voltage scaling (DVS) is a commonly implemented technique to adapt to the wide variance in link utilization, depending on the communication patterns for certain applications. The major limitation with the DVS technique is maintaining sufficient interconnect reliability while scaling the voltages, and the feasibility of generating and distributing multiple variable supply voltages on-chip. [7]

Network Level Techniques

Following from the discussion regarding noise on interconnect reliability from "Why Interconnects Consume So Much Energy", network choice should consider fault tolerance to ensure correct information transfer. Popular techniques for achieving this includes the use of channel coding by using some amount of redundancy in the transmitted data to improve interconnect noise immunity. [9] Error detection on the channel can be handled by either Forward Error Correction (FEC), where one can use the properties of the code to correct the error or by retransmission, also known as Automatic Repeat Request (ARQ). The two schemes were studied in Bertozzi et al., and it was shown that for the same constraint on system reliability, ARQ tend to allow for lower supply voltages compared to FEC and thus is more energy-efficient, despite the larger number of bits being transferred. [10] Finally, data routing algorithms can be implemented at the network layer to optimize the path a message traverses through the network to its final destination for minimum energy consumption.

Architecture Level Techniques

Choice of communication architecture can have significant impact on the system energy and performance. Bus and topology design decisions can change the load capacitance of the bus to be driven, governed by the length of the interconnect segments and sizing of the drivers for the segments. Bus splitting is a widely used technique to reduce capacitive loading during bus transfers, and potentially yield energy savings of 16-50% over a single bus, as well as provides architectural advantages such as parallelism. [11] Other commonly used on-chip network architectures include a router-based architecture, mesh and tree- like networks, and tile-based general purpose interconnection networks. Decisions on which on- chip interconnection network to use is highly dependent on application and exploitation of data locality.

Circuit Level Techniques

On-chip circuit level signaling techniques typically achieve energy reduction by reducing the following factors based on the energy consumption of an interconnect wire in a clock cycle:

Ewire = α × Cwire × Vswing2

In the above equation, is the switching activity of the transmitted signal, Cwire is the capacitance switched during signal transitions and Vswing is the voltage swing across the interconnect wire. Full swing signaling is energy inefficient and thus, a designer can lower the supply voltage and voltage swing to reduce interconnect energy consumption. The downside of using lower voltage swings is decreased circuit reliability and thus, many works consider using differential signaling to improve noise margin and allow for further voltage reduction. Reducing switching activity can also be done by using encoding techniques to limit the number of transitions that cause noise (such as crosstalk) and interconnect delays. [12] The capacitance being switched can also be reduced by using techniques such as twisting of wires coupled with the use of differential interconnects. [13] Implementation of any of these circuit level techniques requires careful consideration of the trade-offs between gains in energy efficiency versus circuit noise and reliability concerns in choosing sizing for the buffers and wires.

Other Considerations

While this report mainly focused on the design space for current CMOS-compatible electrical interconnects, there is a plethora of research focusing on emerging technologies for achieving energy-efficient communication. Examples of this include wireless interconnects, 3D interconnects, and other alternative technologies as Esfandyarpour outlines. [1] Once these new technologies become an industry standard, design optimization of an energy-efficient and reliable interconnect network will require new considerations at the different levels of the system design hierarchy.

© Lita Yang. The author grants permission to copy, distribute and display this work in unaltered form, with attribution to the author, for noncommercial purposes only. All other rights, including commercial rights, are reserved to the author.


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