Energy Consumption in Electrical Interconnects

Majid Esfandyarpour
December 1, 2012

Submitted as coursework for PH240, Stanford University, Fall 2012

Fig. 1: Operating speeds and critical dimensions of various chip-scale device technologies, highlighting the strengths of the different technologies. [5]

During the last few decades the demand for faster information transport led to enormous progress in Si electronics industry. The electronic devices have become smaller faster and more efficient in the last five decades. As the size of CMOS technology continues to decrease the size of the interconnects also scaled with same factor as subsequent result. Decreasing the size of metallic interconnects degrade their performance in a number of parameters including, increase in delay time for signal propagation, power dissipation and cross-talk among the wires. [1]

According to the International Technology Roadmap For Semiconductors the amount of cost effective heat removal from a chip is approaching a limit to be less than 200 W. [2] This inability to remove the heat from the chip limits the performance of the electronic devices. On the other hand Electrical interconnect are consuming more than 50% of the total power consumed by a microprocessor and this ratio is going to increase as the size of the CMOS technology is decreasing in future. [3] Thus reducing the power consumption in electrical interconnect can change the total power consumption of electrical devices substantially. For a quantitative comparison is good to know that in United States, server interconnect power exceeds the total power generated from solar energy in 2007. [4]

In the last few years, finding alternative technologies for the metallic interconnects has become one of the hot research topics in science and industry. Carbon nanotube interconnects, Optical interconnects and 3-D technologies are some of the important and promising suggested solutions to tackle the issues outlined about metallic interconnects. People have also thought about some revolutionary technology like replacing the electrical computation systems with optical computation and transferring form electrical devices to all optical devices. However, the idea of optical computation seems not to happen in near future.

Use of light and optical signal for on-chip communication between electronic processors or replacing the electrical interconnects with optical interconnects seems to be one the most promising solutions to increase the processing speed and decrease the power consumption in metallic interconnects. In an ideal device the computation is done electrically, the electrical signal in converted to optical signals by use of modulators or turning a laser on and off, finally the optical signal at the other end of communication line is reconverted to electrical signal by use of a photodetector.

The Optical components in such a device should be size matched and material compatible with the electronic parts of the circuit. The silicon photonic devices are material compatible with the electronic parts but they suffer from the size mismatch since they are diffraction-limited systems. As a physical law the light cannot propagate in structures that are smaller than half of wavelength of the light. Thus all Si photonic devices should have at least micrometer size to be used in telecom wavelength communication while the electronic parts have nanometer size. This size mismatch between electronic and photonic components presents a major challenge for interfacing these technologies.

Metal nanostructures may be able to overcome this size mismatch outlined above by use of surface plasmon-polaritons (SPP). "SPPs are electromagnetic waves that propagate along a metal-dielectric interface and are coupled to the free electrons in the metal." [5] Surface Plasmon polaritons are not diffraction limited and can be focused and confined to nano-meter scale which is required to connects electronic world to optics world.

Nanoscale waveguides and devices that highly confine electromagnetic waves can be made by use of SPPs. however, the propagation length of surface plasmon polaritons are limited by absorption of light in metal and free-space radiation of SPPs. [6] Some research has been done to increase the propagation length of Surface plasmon waveguides however most of them seems not to be applicable in real devices since there is a trade off between propagation length and confinement of light in plasmonic devices. [6-7]

As it was discussed above photonics devices are material compatible with electronic devices but suffer from size mismatch while the plasmonic devices are size matched but suffer from high loss of the optical signals in metal. So people have proposed a hybrid structure which uses from benefits of both devices palsmonic devices for size matching with electronic, photonic devices for send optical signal over a relatively long distance. [8] In this type of structures the plasmonic modulator will be the interface between the electronics and optics then the optical signal will propagate in a photonics waveguide toward the other end of communication line

This Hyberid architecture of electronics, photonics and plasmonic seems to be very promising, however it need more progress to be used in industry like supporting wavelength division multiplexing.

© Majid Esfandyarpour. The author grants permission to copy, distribute and display this work in unaltered form, with attribution to the author, for noncommercial purposes only. All other rights, including commercial rights, are reserved to the author.


[1] J. Conway, S. Sahni, and T. Szkopek, "Plasmonic Interconnects Versus Conventional Interconnects: a Comparison of Latency, Crosstalk and Energy Costs," Opt. Express 15, 4474 (2007).

[2] "International Technology Roadmap for Semiconductors, 2007 Edition, Executive Summary," ITRS International Roadmap Committee, 2007.

[3] A. Naeemi and J. D. Meindl, "Performance Modeling for Single- and Multiwall Carbon Nanotubes as Signal and Power Interconnects in Gigascale Systems," IEEE Trans. Electron Dev. 55, 2574 (2008).

[4] D. Miller, "Device Requirements for Optical Interconnects to Silicon Chips," Proc. IEEE 97, 1166 (2009).

[5] R. Zia et al., "Plasmonics: The Next Chip-Scale Technology," Materials Today 9, No. 7-8, 20 (July/August 2006).

[6] Grandidier, J. et al. , "Gain-Assisted Propagation in a Plasmonic Waveguide at Telecom Wavelength," Nano Lett. 9, 2935 (2009).

[7] R. F. Oulton et al., "A Hybrid Plasmonic Waveguide for Subwavelength Confinement and Long-Range Propagation," Nature Photon. 2, 496 (2008).

[8] H. M. G. Wassel et al., "Opportunities and Challenges of Using Plasmonic Components in Nanophotonic Architectures," IEEE Trans. Emerging and Selected Topics in Circuits and Systems, 2, 154 (2012).