Chalcogenide Based Phase-change Memory

Sumit Mehra
June 11, 2007

(Submitted as coursework for Applied Physics 273, Stanford University, Spring 2007)


The current class of memories can primarily be classified into SRAM, DRAM and FLASH. None of these technologies provide all the desirable characteristics of an ideal memory, in particular lowest cost, highest speed, long life cycle, lowest power and non-volatility. Chalcogenide phase change memories (PCRAM) or Ovonic Unified Memory (OUM) developed using the class of elements known as chalcogenides is being studied as a candidate for next generation non-volatile memories. The underlying idea is to "unify" all the desirable features of the existing technologies without inheriting any of the unfavorable traits. PCRAM exploits the fact that certain alloys of group V or group VI elements in the periodic table, known as phase change elements can be made to switch reversibly between their crystalline and amorphous states with the application of electric current.


Fig. 1: Schematic cross section of the device structure. Note the thermal cross-talk between the adjacent bits.

Using a thin-film of chalcogenide alloy material (Ge2Sb2Te5-GST), the two states of the alloy, polycrystalline (composed of many crystals, each having atoms placed in a repetitive order) and amorphous (no long-range order of atoms) each represent a single logic state thus storing data. Reversible phase transitions between these two states take place with the application of heat to the active media region in each cell [5]. Fig. 1 shows the cross-section of an OUM cell array [3]. The heat required for the phase change is generated by passing electric currents of different magnitudes through the heater (emitter) into the GST layer. Local joule heating is used to change the programmable volume around the contact region. The phase switching of Ge2Sb2Te5 triggered by Joule resistive heating (qJoule), is given by:


where, IF is the external forcing current, R is the electrical resistance of the Joule heating material, and t is the heating time. Also, R is given by R = ρelec . L/A, where ρelec is the electrical resistivity, L is the length, and A is the cross-sectional area of the Joule heating material, respectively. The cell essentially acts as a fast programmable resistor that changes resistance by several orders of magnitude (with greater than 40X dynamic range) depending on whether the programmable chalcogenic material is in the crystalline or the amorphous state.

Fig. 2: Chalcogenide programming.

Programming or writing to the memory (Fig. 2) [4] requires a large current known as the RESET current, in order to heat up the chalcogenic material accompanied by fast quenching, leading to a local amorphous phase with high resistance. The time associated with this switching is typically 10-30 nsec, and the thermal time constant of the cell structure is typically a few nsec only. Temperature profiling shows that only a small amount of material around the contact region is heated to above 650C, sufficient to change the programmable volume to amorphous state [2]. The temperature drops off quickly and no significant thermal cross-talk has been observed at the 65nm technology node. This keeps the material at the adjacent cell intact in its local amorphous or crystalline form.

To re-crystallize the region, a medium current with a longer pulse time is passed. This crystalline state has low resistance. To perform a cell readout, a significantly lower current with no heating is required, differentiating between the low resistance (crystalline) and high resistance (amorphous) states (Fig. 3 [6]). A negative resistance is observed when the GST material switches from the off state (high resistance) to the on state (low resistance) used for programming. Fig. 4 shows the basic IV curve of the device. If the device current exceeds the minimum level, the IV curves are same independent of the phase of the material or the initial memory state. This gives it direct write capabilities without the need of first erasing previously stored states (like in flash memory), simplifying writing and improving the write performance. Also above a certain threshold voltage Vth the two states switch to a low resistance state independent of the material phase. This switching does not change the structural phase of the material and the resistance values are restored once the voltage is dropped back to the holding voltage (VH).

Fig. 3: (a) The resistance of a SET state (b) reset state for the read operation of a PCRAM. Here Rc is the current resistance, ρc and ρa are the electrical resistivities of the crystalline and amorphous phases of Ge2Sb2Te5, respectively, x is the programmable thickness, l is the total length and A is the cross-sectional area of the Ge2Sb2Te5 layer.
Fig. 4: IV curve of basic memory element.

The Switching Process

The switching process of the chalcogenide alloy can be best analyzed using the nucleation theory where the rate is dependent on the applied voltage [1]. The conduction and switching characteristics depend on the structures of the disordered and the amorphous material. This in turn is related to the local bonding characteristics of the constituent elements. A high density of localized states in the forbidden energy gap is split from the conduction and valence bands by the translational and compositional disorder. The disorder allows most atoms to complete their valence state and thereby establish a high degree of compensation, yielding the observed behavior of these materials. A large overlap in energy of those levels in the valence band with those from the conduction band is expected with self-compensation of charges producing a large density of traps. These traps when occupied can easily be ionized at moderate fields by lowering the trap depth and reducing the capture cross section. A rapid increase of carrier concentration results, and can explain the observed non-ohmic behavior in the low-conductivity state.

The relatively close spacing of these localized states in both space and energy makes it likely that the internal-field ionization and emission play an important role in the carrier generation necessary to initiate the conducting state at threshold field values of the order 105 V/cm. The low mobility and high number of localized states offer, in principle, the possibility of the dramatic conductance changes observed. Once the switching takes place, a redistribution of carriers as a result of oppositely charged carriers having very different mobilities and transition rates through the electrode interfaces gives rise to a space charge and field enhancement near one electrode and to the small value of Vh.

Reducing Switching Current

One of the main concerns for making PCRAM as a desirable memory alternative is the high switching current. The switching (reset current) has been recorded to be 1 mA based on 180 nm lithography [2]. For all practical applications, the desirable range should be below a few hundred µA. The reset current scales almost linearly by reducing the device contact area and with lithography scaling. Two innovative ideas being researched for reducing the reset current are:

Edge Contact: As shown in Fig. 5 using edge contact reduces the reset current. [3] This can be attributed to the increase of the heater thermal resistance with the diminishing of the contact area which is determined by a thin film thickness in one dimension. Joule heating mainly takes place inside the GST, where voltage is close to the holding voltage (Vh). Since the melting temperature is constant and as the heater thermal resistance increases the power required to melt the programmable GST decreases. As power is P = Vh I, a reduced current requirement follows.

Nitrogen Doping: Another idea for improving the reset current is to dope the chalcogenide material with nitrogen [2] thus achieving a higher resistance material requiring reduced reset current. This process is derived from research work on rewritable optical disks which also uses the difference in reflectivity of chalcogenide material in its amorphous and crystalline form for defining two logic states and storing data.

Fig. 5: Edge contact to reduce switching current.

GST memory elements show tremendous promise due to decreasing cell size and lower cost per bit by storing multiple bits per memory element. The transition in resistance between the low and high resistance states can be achieved in several small steps instead of one abrupt transition. [3] Current efforts have been able to break down this transition into 16 discrete steps corresponding to different resistance values, indicating 4 bits could be stored per memory element instead of the traditional 1 bit per memory element.

© 2007 Sumit Mehra. The author grants permission to copy, distribute and display this work in unaltered form, with attribution to the author, for noncommercial purposes only. All other rights, including commercial rights, are reserved to the author.


[1] S. R. Ovshinsky, "Reversible Electrical Switching Phenomena in Disordered Structures," Phys. Rev. Lett. 21, 1450 (1968).

[2] S. Lai, "Current status of phase change memory and its future," IEDM Tech. Dig. [Proc. of the 2003 International Electron Devices Meeting, Washington, D.C. ] (IEEE, 2003), p. 255.

[3] Pirovano et al., "Scaling Analysis of Phase-Change Memory Technology," IEDM Tech. Dig. [Proc. of the 2003 International Electron Devices Meeting, Washington, D.C. ] (IEEE, 2003), 699.

[4] Maimon et al, "Chalcogenide-Based Non-Volatile Memory Technology," IEEE Aerospace [Proc. of the 2001 IEEE Aerospace Conference] 5, 2289 (2001).

[5] M. Wuttig, "Phase-Change Materials, Towards a universal memory," Nature Mat. 4, 265 (2005).

[6] D.-H. Kang et al., "One-dimensional heat conduction model for an electrical phase change random access memory device with an 8F2 memory cell (F = 0.15 µm)," J. App. Phys. 94, 3536 (2003).