High Permittivity Dielectrics for Nano-scale Devices

Eunji Kim
March 24, 2007

(Submitted as coursework for AP272, Stanford University, Winter 2007)

Fig. 1: Cross-sectional view of a MOS device.
Fig. 2: TEM cross section of SiO2 gate oxide with physical thickness of 1.2nm, from Chau [1].

These days all the electronic devices become smaller, thinner and lighter. They are even faster and more cost eligible than before. This new technology has been enabled by aggressive device scaling during the last few decades.

Why High-K?

One of the important parameters determining the performance of a MOS (Metal-Oxide-Semiconductor) device, such as that illustrated in Fig. 1, is the drive current. In order to get a higher drive current, we must either decrease the channel length or increase the gate capacitance. The latter is given by

C = ε0KA/Tox

where ε0 is the permittivity of free space, K is the relative dielectric permittivity, A is the area under gate electrode and Tox=gate oxide thickness. We would specifically like to decrease Tox.

SiO2 has been conventionally used as a gate oxide in MOS devices; however, when its thickness is reduced to 2nm, the leakage current through SiO2 increases considerably by direct tunneling. We have already passed the 90nm technology node (shown in Fig. 2), and we are approaching the 45nm node which requires even thinner gate oxides. In 1997, Y. Taur et al. reported the trend of increasing gate leakage current across SiO2 with decreasing gate oxide thickness (Toxide) (shown in Fig. 3). The horizontal dashed line in Fig. 3 represents the limit of the tunneling current for device reliability and acceptible power dissipation. Therefore, instead of decreasing Tox, using high-K dielectrics as alternatives to SiO2 in order to achieve a higher gate capacitance has been studied by many research groups.

Fig. 3: Measured and simulated gate leakage current density, from Lo et al. [2]

Requirements for Alternative Gate Dielectrics

There are several requirements for the choice of a new gate oxide. First, the gate oxide must have a high dielectric constant to induce a higher charge in the channel. Second, it must be thermodynamically stable with the underlying channel material such as Si. Otherwise, it will react with the underlying substrate resulting unwanted byproducts such as SiO2 which would decrease the effective gate capacitance. Third, it must have a wide band gap and band offsets to suppress the leakage current. Fourth, it must be kinetically stable at high temperatures to be compatible with the semiconductor device fabrication process. Finally, it must have a clean interface with the channel materials to achieve a high breakdown voltage and low interface and bulk trap densities. Among the possible candidates, Hf-base dielectrics (e.g. HfO2) have received increasing attention because they exhibit good electrical properties meeting the requirements listed above quite well compared with other candidates.

High-K Growth Methods

There are many possible methods to grow high-K dielectrics on the channel materials such as sputtering, chemical vapor deposition, etc. Some of the popular high-K deposition methods are compared in terms of coverage, purity, and so on (Table 1). In ALD (Atomic Layer Deposition) process, one of the most promising deposition methods for high-K, films are grown layer by layer. As shown in Fig. 4, once metal precursors arrive on the subrate and they are adsorbed on the surface of the substrate, the reactor is purged with an inert gas so that only a monolayer of adsorbed precursors is left on the substrate surface. Then, oxidants such as H2O vapor carried by an inert gas arrive on the surface, and react with the adsorbed metal precursors. By this cyclic process, the amount of materials deposited in each cycle is uniform. Therefore, accurate control of film thickness and excellent step coverage are achievable by ALD process.

Coverage Purity Defects Thickness Large Area
Sputtering O OO XXX OO
Metal dep + Oxidation O OO O OO OOO
Table 1: Comparison of deposition methods. O=good, X=bad. After Robertson [3]
Fig. 4: Schematic of atmoic layer deposition. (Courtesy of P.C. McIntyre)

Recent Achievements and Future Technology Utilizing High-K

Promising electrical and physical characteristics of high-K dielectrics deposited on various semiconductor channel materials (e.g. Si, Ge, IIIV) have been reported. They exhibit low leakage current, high dielectric constant, smooth interface with the channel materials[4],[6]. Increasing attention on high mobility channeal materials such as Ge, IIIV compound semiconductors has opened more opportunities to high-K dielectrics as gate oxides. Figure 5 shows a TEM cross-section image of a SWNT (Single-Walled Carbon Nanotubes) on SiO2 covered with 4-nm-thick ZrO2. Besides changes in the structure of the device, from the point of view of materials science, high-K dielectrics combined with high mobility channel materials are crucial for continuing device scaling.

© 2007 Eunji Kim. The author grants permission to copy, distribute and display this work in unaltered form, with attribution to the author, for noncommercial purposes only. All other rights, including commercial rights, are reserved to the author.

Fig. 5: TEM image of the cross-section of a SWNT on SiO2 with conformal coating of 4-nm-thick ZrO2. After Javey et al. [5].


[1] R. Chau, "Advanced Metal Gate/High-K Dielectric Stacks for High-Performance CMOS Transistors", ICMI, 2004.

[2] S.-H. Lo et al., "Quantum-Mechanical Modeling of Electron Tunneling Current from the Inversion Layer of Ultra-Thin-Oxide nMOSFETs", IEEE Elec. Dev. Lett. 18, May 1997.

[3] J. Robertson, "High Dielectric Constant Oxides", Eur. J. Appl. Phys. 28, 265 (2004).

[4] D. H. Triyoso ete al., "Film Properties of ALD HfO2 and La2O3 Gate Dielectrics Grown on Si with Various Pre-Deposition Treatments", J. Vac. Sci. Tech. B. 22, 2121 (2004).

[5] A. Javey et al., "High-K Dielectrics for Advanced Carbon-Nanotube Transistors and Logic Gates", Nature Mat. 1, 241 (2002).

[6] H. Kim et al., "Characteristics of ZrO2 and HfO2 Grown by Atomic Layer Deposition", J. Mat. Res. 20, 3125 (2005).